The present invention relates to a chip carrier, and more particularly, pertains to a chip carrier constituted of an organic laminate which incorporates structure compensating for thermal deformation of the carrier. Moreover, the invention relates to a method of counteracting the thermal deformations encountered by chip carriers, especially during solder reflow, which is predicated on the positioning of metal-plated through-holes (PTH) formed in the chip carrier.
In considering the structure of chip carriers, such as flip chip attach carriers, especially those which are constituted of organic laminates, the positioning of the plated through-holes (PTH) which provide for electrical interconnections between different printed circuit layers, the mismatch which is present in the thermal expansion (CTE) between the plated through-holes, in which the metal plating in the holes normally comprises copper, and the organic laminate material of the printed circuit board (PCB) or carrier, frequently results in both in-plane and out-of-plane thermal deformations of the carrier during solder reflow operations, which have an adverse effect on the reliability of the electrical connects at the locations of ball grid array (BGA) pads. In essence, the irregular or random spacings of the plated through-holes (PTH) with regard to the ball grid array (BGA) pads has evidenced that the closer the proximity of the plated through-hole to a BGA pad, this considerably increases the thermal deformation of the chip carrier at the location of the pad, adversely affecting product reliability through potential failures of the electrical connections at the pad position as a consequence of warpage of the organic material of the chip carrier.
Although publications presently address themselves to various problems associated with different types of arrangements of through-holes and vias extending through chip carriers, these generally do not concern themselves with compensating for thermal deformation stresses or strains tending to deform chip carrier, especially during solder reflow due to differentials or mismatches in the thermal expansion (CTE) which are present between the plated through-holes (PTH) and that of the organic laminate material of the chip carrier having the BGA pads thereon.